There are many applications for memory devices capable of storing large amounts of data in a nonvolatile way, to be provided to or made accessible at a later time to a processing system. Typical examples are memory devices for PCBios applications on PCI buses, for digital cameras, electronic agendas, measurement instruments, electronic appliances of vehicles and the like. At the present time, the type of memory devices that are most used in these applications are the so-called FLASH memories.
Independently from the protocol used for writing a byte of data in a FLASH memory, the following steps are performed: a first protocol cycle for unprotecting the sector or sectors of the matrix of memory cells in which data bits are to be written; a second protocol cycle for communicating the write command to the memory; a third protocol cycle for providing the address of the memory sector to be written, and the relative data byte; and carrying out a memory write algorithm for the data byte to be stored in the memory.
Depending on the protocol used, each cycle includes distinct phases, during which address bits and data bits or bits of command codes are sent to the memory alternated with synchronization bits, but substantially the data bits are written in the memory by performing the above mentioned steps. To better explain the technical problem being addressed herein, reference will be made hereinafter to an LPC communication protocol, though the same considerations are also valid, with appropriate changes, for all the protocols in which the writing of a data byte is carried out in the above mentioned way, such as the communication protocols between memory and processor on a motherboard.
FIG. 1 depicts a typical write cycle of LPC protocol during which an address and a relative byte to be written are input to the memory. The start phase START lasts a clock period CLK and is determined by the switching of an external command LFRAME. A phase CYCTYPE follows, which also lasts a clock period, during which it is specified whether the protocol cycle is a read (READ) or a write (WRITE) cycle, as in the shown example. During a third phase ADDR, which lasts 8 clock periods, the address bits of the sector to be written are transmitted in groups of 4 bits. Then three phases, namely: DATA, TAR and SYNC, are carried out, in a total of 5 clock periods, during which the memory receives the byte of data to be written and confirms that it has been received. Finally, with the last phase TAR, which lasts two clock periods, the memory device releases the control of the system bus that connects it to the external world.
On the whole, a write cycle of an LPC protocol lasts 17 clock periods and only one byte of data to be written is transmitted. Even an LPC protocol cycle for communicating to the memory device the codes of a command to be executed lasts 17 clock periods. Therefore, in known devices implementing an LPC protocol, for writing a certain number of bytes, it is necessary to repeat the above mentioned two cycles of protocol and the write algorithm for each data byte to be written. In practice, 34 clock periods plus the time taken for carrying out the write algorithm and unprotecting the memory sectors to be written on are necessary for each single byte.
Neglecting the time needed for unprotecting the memory sectors of interest, and supposing that a clock period last 1 μs, using a 1 Mhz programmer, and supposing that the write algorithm last 10 μs, to write a single data byte in the memory(2*17*1+10)μs=44 μs  (1)are necessary. This write (programming) time of a single byte is relatively long. Considering that standard FLASH memory devices have usually a capacity in the order of Mbytes, programming a whole array of FLASH memory cells is a relatively long operation.